URSI™ - Universal Responsive Serial Interface

The world’s lowest 3.5x oversampling asynchronous serial communication scheme. Without PLL it offers ±20% jitter tolerance, immediate responsiveness, and ultra low standby power.

Industrial - Upgrade RS-485 into an IP-capable network with legacy support

Seamlessly support existing ModBus equipment on the same port while migrating to a modern IP capable network.

Bridge legacy Modbus and future URSI™/IP networks on the same twisted pair. Standard RS-485 is limited to 10 Mbps over short distances and lacks native IP support. URSI™ delivers 10 Mbps over 100 metres with low overhead framing for efficient IP packet transport, while its ±20% clock/jitter tolerance ensures reliable operation.

• MeshDAQᵀᴹ Measurement and Automation for Industry & Residential: A distributed data acquisition and control system where URSI™ provides power, reliable communication, and a scalable mesh fail-safe architecture across a single twisted pair

• Quartz-less sensors: Reliable interfacing with RC oscillator-based sensors under wide temperature stress

• Building automation: Low-cost sensors and control over extended distances.

Neuromorphic & Event-Driven - Low-power responsive AER link

Address-event representation (AER) links spend most of their time idle. PLL-based links burn constant power. URSI™ consumes near-zero power in standby, wakes on the first edge, and resynchronises instantly, making it ideal for neuromorphic chips, event-based sensors, and spiking neural networks (SNN).

• Requires single line or differential pair to connect neuromorphic devices.

• Can carry power supply over a single differential pair.

• Low latency, high reliability, low power consumption.

Embedded - Fast, low-cost chip-to-chip communication without SERDES

SPI and I²C are distance- and speed-limited. High-speed SERDES requires PLLs and complex PHYs. URSI™ offers a PLL-free, all-digital alternative with a tiny footprint.

• FPGA to FPGA, FPGA to MCU, general low power and low cost inter-connectivity.

• Easily clocked at 400 MHz in a typical FPGA, delivering 100 Mbps links. With double data rate (DDR) on LVDS I/O it achieves 200 Mbps.

• A single isolation barrier can carry both data and clock, simplifying isolated interfaces (e.g., medical, industrial control).

• Ideal as a low-latency debugging trace interface.

Comparison Table

Modulation	Max Speed	Signal Bandwidth	Clock/Data Recovery	Clock Tolerance	Idle to 1st Bit	Complexity / Cost
URSI™	Gbps	>0.6 x rate	>3.5x Oversample	Typical ±20%	<3 bits	Low
USB Full-speed	Mbps	0.6 x rate	4x Oversample	±0.2% + Preamble	<10 bits	Medium
Manchester	Gbps	1.0 x rate	5x Oversample, PLL	Preamble Sync	2..64 bits	Low / Medium
NRZI UART	Mbps	0.6 x rate	8..16x Oversample	±2%	<3 bits	Low
NRZI + 8b10, …	Gbps	0.6 x rate	PLL CDR	Preamble Sync	<80 bits	Higher